PMC-based FPGA
Product
Processor(s)
Memory
I/O
Ruggedization
Xilinx Virtex-5 LX110T/SX95T FPGA
Dual banks of 36b QDR2 SRAM and 16b DDR2 SDRAM memories
N/A
AC L0, AC L100, CC L100 (contact factory for availability)
Xilinx Virtex-II Pro XC2VP50
2x 64MB DDR SDRAM, 3x 2Mx18-bit QDR-II SRAM
138 Signals to front panel or RocketIO to front panel, 64-bit 66MHz PCI, 64-bit User I/O on PMC P14
AC 0
Xilinx Virtex-II Pro XC2VP50
2x 64MB DDR SDRAM, 3x 2Mx18-bit QDR-II SRAM
4 fiber-optic on front panel, 64-bit 66MHz PCI, 64-bit User I/O on PMC P14
AC 0
Xilinx Virtex-5 LX110 or LX155 FPGA
Multiple banks of SRAM for DSP; Multiple banks of SDRAM for large buffers
Customizable digital I/O
N/A
Xilinx Virtex-5 SX95T
Two banks of 9Mbytes 250MHz QDR2 SRAM memory; Two banks of 128Mbytes 250MHz DDR2 SDRAM memory
Range of front panel I/O personality modules (including ADC, DAC, LVDS, RS-485/422 and Camera Link)
N/A
Xilinx VP40
Up to 256 MB DDR SDRAM
33/66 MHz PCI, 2.5 GB/sec Front-panel RocketIO, 2 GB/sec Rear-panel RocketIO, 30-bits front-panel LVDS/LVTTL (15 pairs), 48-bits rear-panel LVDS/LVTTL (24 pairs)
AC 0, AC 100, CC 100, CC 200
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