PMC-FPGA05 Virtex-5 FPGA PMC

The PMC-FPGA05 is a Xilinx Virtex-5 XC5VLX110 or XC5VLX155 platform FPGA based, PMC module with high speed digital I/O and PCI-X interface to the host computer. The PMC-FPGA05 is aimed at embedded application development and deployment..

Xilinx Virtex-5 FPGA
The Virtex-5 XC5VLX110 or XC5VLX155 FPGA is configured from FLASH. A default image which instantiates the PCI-X interface and Flash programming interface is preloaded into the FLASH along with a recovery image which cannot be overwritten. There is space for 3 or more configurations and the image used is selected by switch.

Digital I/O
There are 138 signals routed to a 180-way connector near the front panel. These lines are routed so that they may be used as single-ended signals or differential pairs. The FPGA I/O signals are banked, with two banks being used at the front panel connector. Each bank is independently configurable to 2.5V or 3.3V signaling.

Developers can create custom modules suited to their application as we supply complete specifications for these modules with the documentation that comes with the board.

Another bank of 64 single-ended lines (32 differential pairs) connects to P14, the PMC user I/O connector, to support rear I/O.

Memory
By default, three banks of 9 Mbytes each QDR II SRAM support DSP functions in the Virtex-5 and are independently connected to the FPGA, providing great flexibility in how they are used. The SRAM is clocked at 200MHz, providing simultaneous read and write operations each at 800Mbytes/s. Two independent banks, each with 128 Mbytes per second DDR2 SDRAM, are directly connected to the FPGA. Clocked at 200MHz, each bank can be used independently (e.g. filling one memory while emptying data from the other at 800Mbytes/s) or as a single 32-bit wide, 1600Mbytes/s memory structure. This memory provides a large pool of memory to buffer DMA transfers and other large data block operations.

Flash
The Virtex-5 FPGA is configured from a 256Mbit (32Mbytes) on-board FLASH. A default configuration image, with a PCI-X interface and Flash programming interface, is preloaded into the FLASH along with a recovery image. The FLASH is programmable through the PCI/PCI-X bus. Three or more Virtex-5 configurations can be held in the FLASH. The image used to configure the FPGA is selected by switch.

Software/HDL code 
The PMC-FPGA05 is supported under the Windows XP, VxWorks and Linux. The BSP includes:

• VHDL library code blocks (demonstrating how board resources can be used) Windows XP drivers
• API with C support libraries
• Example code
• FLASH programming and board debug utilities
• Hardware and software manual

Development of VHDL code for the FPGA requires synthesis tools such as Xilinx ISE Foundation.