AD1520 1.5GSPS 8-bit ADC

The AD1520 is a second generation 1.5GSPS ADC XMC module and follows on from the AD1500. The AD1520 uses a newer generation ADC device and key benefits include increase full power bandwidth (from 1.5 to over 2GHz) and general improvement in ENOB, SFDR and SNR.

The AD1520 closely couples a high performance Xilinx Virtex-5 FPGA to a dual channel high-speed analog input front end providing both processing and up to 1.5GSPS acquisition (per channel) in a single XMC/PMC card. The combination of a user programmable FPGA, data I/O sub-systems and multiple banks of fast memory provides a powerful platform for acquiring and processing high-speed data in one board. In addition to processing digitized data, the Xilinx Virtex-5 SXT or LXT FPGA is used to control the analog to digital converter and provides the off-board interfaces to either PCI-X or the multi-Gbps serial I/O used for the XMC interface.

The AD1520 is ideal for DSP applications including: Electronic Warfare (EW), Electronic Counter Measures (ECM), Spectral Analysis and Radar

Analog I/O and FPGA Processing in One
The AD1520 is a combined acquisition and FPGA based data processing module. The majority of the Virtex-5 FPGA resources are available for user programmable processing and are supported by SRAM and SDRAM memories. Some applications that are ideally suited for FPGA based processing include Digital Down Conversion (DDC), Fast Fourier Transforms (FFTs) and digital filters.

1.5GSPS Analog Input
Analog to digital conversion is performed by a National Semiconductor ADC08D1520 device, which is a dual channel 8-bit, 1.5GSPS ADC. The analog input stages are transformer AC coupled to the ADC via a balun. Using the ADC's built-in demultiplexer, digitized data is transferred to the FPGA using an interleaved 32-bit interface (2+2 samples in parallel) along with a half of clock frequency to match valid data.

Clocks, Triggers and Multi-board Synchronization
The AD1520 provides a front-panel MMCX connector for connecting an external sample clock source (required).

A front panel mounted trigger input (TI) and a trigger output (TO) signal are connected to the FPGA via LVPECL I/O stages. This allows the FPGA to define the trigger mechanism through the application for maximum flexibility.

The AD1520 supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source. When synchronized, all data will be aligned and coherent across multiple AD1520 boards. Curtiss-Wright's XCLK1 clock generator is capable of providing this synchronized sample clock output to two or more AD1520 ADCs, providing support for features such as synchronous reset of the sample clock.

Xilinx Virtex-5 FPGA
The AD1520 can be fitted with either a Xilinx Virtex-5 SX95T or LX110T FPGA (contact factory for alternative FPGA variants) allowing the AD1520 to be optimized to provide the largest amount of DSP capabilities or maximum amount of logic gates.

The FPGA is configured at power up from FLASH with a default image, a recovery image or an image the customer generates. In addition to FLASH configuration, new images can be downloaded from the host via the PCI or PCI Express interface. Software is provided to load new images into either FLASH or SRAM. Bit streams stored in SRAM benefit from faster downloads while bypassing non-volatile storage - useful for secure applications.

Multiple SDRAM and SRAM Banks
The AD1520 features both external SRAM and SDRAM connected to the FPGA. These can be used for buffering ADC data or for general purpose processing support.

The two 64M x 16-bit DDR2 SDRAM banks on the AD1520 can be used in parallel to buffer digitized data.

QDR2 SRAM provides higher bandwidth external memory. Two 2M x 36-bit banks are fitted on the AD1520. Interleaved, the QDR2 SRAM banks have sufficient bandwidth to store and retrieve data at the maximum 3GSPS data rate.

PCI/PCI-X, PCI Express and Multi-Gbps I/O
The AD1520 includes a PCI/PCI-X interface and a PCI Express interface. These interfaces provide multi-channel DMA support.

The PCIe interface uses the Virtex-5 FPGA's RocketIO™ GTP transceivers and an embedded end-point controller, which is a hard IP block within the Virtex-5 FPGA. This built-in PCIe endpoint block supports x4 or x8 lane communications at 2.5Gbps according to the PCIe standard, but can be bypassed to support other protocols like sFPDP or sRIO. Overall, the Virtex-5 FPGA provides sixteen, full duplex high-speed serial communication links through RocketIO GTP transceivers. These links are evenly split between two XMC (VITA 42) connectors, with each link capable of operation at up to 3.2Gbps (using an SX95T FPGA) and can be driven as independent data streams or bonded to create 'fat pipes' for fewer, but higher bandwidth, data streams.

Rugged Build Options
A range of environmental requirements are addressed by the AD1520: air-cooled benign, air-cooled extended temperature, air-cooled rugged and conduction-cooled. For conduction-cooled applications, the host board must be able to incorporate front panel I/O connections. Depending on the application, a suitable heatsink may be required for conduction-cooled builds.

FusionXF Software/HDL Support
Curtiss-Wright's FusionXF development kit includes software, HDL and utilities with examples and infrastructure for using the AD1520 or the AD3000 on one of our other Xilinx Virtex-5 and Virtex-4 FPGA-based products. FusionXF includes a C-API and sophisticated DMA support.

FPGA
Device	Xilinx Virtex-5 LX110T or SX95T (speed grade 2)
DDR2 SDRAM	2 banks of 64M x 16-bit (2 banks of 128MB)
QDR2 SRAM	2 banks of 2M x 36-bit (2 banks of 9MB)
FLASH	1Gbit (FPGA boot/configuration including rescue image)
Analog Input
Number of Channels	2, single-ended
Sampling Frequency	Up to 1.5GSPS
Full Scale Input Voltage	600-800 mV (programmable)
Device	ADC08D1520
Full Power Input Bandwidth	2.0GHz
Input Impedance	50 Ohm, AC Coupled
SNR (device)	47 dB *
SFDR (device)	61 dBc*
ENOB (device)	7.4 bits*
Clock & Trigger Inputs
External	Front panel MMCX
Sample Frequency Range	200MSPS to 1.5GSPS
Input Level	600-1800mV (sine or squarewave)
Input Inpedance	50 Ohm, AC coupled
Trigger/Input/Output	Single-ended, 50 Ohm, LVPECL, DC Coupled
PCI
PCI Compliance	32/64-bit PCI 33/66 MHz, PCI-X 66/100 MHz Master/slave/DMA, Interrupt support
XMC
XMC P15	8x RocketIO @ 3.125Gbps or 8x PCI Express
XMC P16	8x RocketIO @ 3.125Gbps
Software/Firmware
Host Drivers	Windows, VxWorks, Linux
Utilities	FLASH programming, diagnostics
Software/HDL Code	Analog input, memory interfaces, PCI-X, PCI Express
Miscellaneous
Weight	Commercial air-cooled 113g Rugged air-cooled 150g Conduction-cooled 141g

 

 

Documents

AD1520 datasheet

Other Links

Ruggedization Levels Product Group Index ADC510 ADC511 ADC512 ADC513 FusionXF FPGA Development Kit