XMC-FPGA05F Virtex-5 FPGA XMC

Xilinx Virtex-5 FPGA
The XMC-FPGA05F is designed to be a user programmable FPGA resource and can be supplied with a choice of Xilinx Virtex-5 FPGAs including SX95T or LX155T (-2 speed grade) parts. The choice of FPGAs allows the XMC-FPGA05F to be optimized to provide the largest amount of DSP capabilities or maximum number of logic gates.

The FPGA configuration can be updated and controlled by the host across the PCI/PCI-X or PCI Express (PCIe) interfaces using the FLASH memory to store images. The host issues commands over the PCI/PCIe interface to cause FPGA reconfiguration from any of the stored images. A 'FLASH bypass' mode can be invoked which uses temporary storage in SRAM, instead of FLASH, to provide the FPGA configuration. A bit stream stored in SRAM benefits from faster downloads while bypassing non-volatile storage - useful for secure applications.

Fiber-optic I/O
Up to four full duplex 'low-rider' Stratos Optical Technologies fiber-optic transceivers can be fitted to the XMC-FPGA05F for front panel connections. The transceivers can be supplied in frequencies ranging from 1.0625 to over 3Gbps with single and multi-mode options. Each transceiver is driven directly by an FPGA RocketIO™ high-speed serial (HSS) link and gives the developer full control over the fiber-optic data protocol. The flexibility of the XMC-FPGA05F even allows different protocols on different channels, such as Serial FPDP (sFPDP) and Aurora™, to be used at the same time.

Multiple Memory Banks
The XMC-FPGA05F features four banks of DDR2 SDRAM connected to and controlled by the FPGA. The memory banks are available to the developer to use for any purpose. Each memory bank can, for example, be associated with each of the four fiber-optic data streams as large independent data buffers dedicated to each channel, used for look-up tables or DSP processing. Each of the SDRAM banks has a capacity of 128Mbytes and provides a 16-bit data path. When clocked at 250MHz, each SDRAM bank is capable of bandwidths approaching 1Gbyte/sec.

PCI/PCI-X, PCI Express & Multi-Gbps I/O
The XMC-FPGA05F includes a PCI/PCI-X interface, supporting up to 133MHz operation, and a PCIe interface. Depending on the interface being used, the board provides at least four DMA controllers. The PCIe interface uses the Virtex-5 FPGA's RocketIO HSS transceivers and an embedded end-point controller, which is a hard IP block within the Virtex-5 FPGA. The built-in PCIe end-point block supports x4 or x8 lane communications, but can be bypassed to support other protocols like Aurora, sFPDP or Serial RapidIO^® (sRIO). Protocols like Aurora provide low latency communications at high-speed and can be used as either x1, x4 or x8 wide data paths.

Digital I/O
Although the XMC-FPGA05F is intended for high-speed serial I/O and FPGA processing applications, it is also equipped with 64-bit digital I/O that can be used as high-speed differential or single-ended I/O including LVDS. The 64-bit digital I/O is provided through either the board's PMC P14 or XMC P16 connectors connected directly to the FPGA. The choice of P14 or P16 connector I/O is defined through a build option.

FusionXF Software/HDL Support
Curtiss-Wright's FusionXF development kit includes software, HDL and utilities complete with examples for using the XMC-FPGA05F. FusionXF is a common environment used across our Virtex-5 FPGA-based family of products. FusionXF includes a C-API, driver framework and sophisticated DMA support. One of the core elements to the FusionXF development kit is a framework for adding in new IP functionality or capabilities to the FPGA easily and effectively. Example software/HDL illustrates how to interface to onboard devices such as fiber-optics, PCI, PCIe, DDR2 SDRAM and XMC interfaces.

Software utilities are provided for configuring the FPGA. These include FLASH programming and commands to configure the FPGA from a given image in FLASH. The FPGA may also be configured via a 'FLASH bypass' mode or ChipScope™ Pro/JTAG interface. Host operating systems supported by the FusionXF suite includes Windows, VxWorks and Linux.

Rugged Build Options
A range of environmental requirements are addressed by the XMC-FPGA05F including commercial, air-cooled rugged and conduction-cooled. For conduction-cooled applications, the host board must be able to incorporate front panel I/O connections. Depending on the application, a suitable heatsink may be required as the FPGA is capable of dissipating high power for demanding applications.

FPGA
Device	Xilinx Virtex-5 SX95T (default), or LX155T (contact factory for availability of FX100T build) Speed grade 2
Configuration	Over PCI, PCI-X or PCIe interface - 1Gbit FLASH (FPGA boot/configuration including rescue image) - FLASH bypass - images stored in SRAM - JTAG/ChipScope pro port
Memory
Type	DDR2 SDRAM clocked at 250MHz
Capacity	Total: 512Mbytes Arranged as four banks, each 64M x 16-bit
Fiber-optic interface
Number of transceivers	2 or 4 full duplex transceivers connected to FPGA RocketIO HSS
Connector	LC (contact a sales representative for alternatives) single-mode and multi-mode
Transceivers	2.5 and 3.125Gbps 850nm, multi-mode Contact a sales representative for alternative speeds and single-mode
PCI and PCI-X interface
PCI Compliance	PCI 33/66MHz, PCI-X 66/100/133MHz Master/slave/DMA, Interrupt support 3.3V VIO only
PMC P14 User I/O	64-bit I/O arranged as 32 differential pairs connected directly to the FPGA (Note: this is a mutually exclusive build option with XMC P16 I/O)
XMC interface
Compliance	VITA 42.0
XMC P15	8x RocketIO GTP @ up to 3.75Gbps (LXT/SXT) or x4/x8 PCIe release 1.1
XMC P16	64-bit I/O compliant with VITA 46.9 X20d24s connected directly to the FPGA (Note: this is a mutually exclusive build option with XMC P16 I/O)
Software/HDL
Host Drivers	Windows XP, VxWorks, Linux
Support/Utilities	FusionXF development kit FPGA/FLASH programming, diagnostics
HDL examples	Fiber-optic I/O (RocketIO), memory interfaces, PCI-X, PCIe, data DMA
Miscellaneous
Weight	TBA
Power	TBA
MTBF	TBA

Other Links

Ruggedization Levels Product Group Index FusionXF FPGA Development Kit