|
|
MM-7110 PMC Dual Virtex-4 FPGA
PMC FPGA Compute Node with User Programmable Virtex-4 LX200 and SX55 FPGAs
- Utilizes the largest Xilinx Virtex-4 LX and Virtex-4 SX FPGAs
- Most FPGA Logic resources and DSP resources ever to be offered on a PMC form factor
- Optional CoSine FPGA IP and Development Kit provide totally preconfigured, fully tested infrastructure for rapid development time
- Virtex-4 LX200 CoSine Primary Device
- Virtex-4 SX55 CoSine Companion Device
- 512MB or 1GB DDR2 memory with ECC
- PCI/PCI-X bus interface that operates in 32-bit or 64-bit PCI mode @ 66MHz or 64-bit PCI-X mode @ 66MHz or 133MHz
- Inter-FPGA interconnect supports over 3GB/s of full-duplex bandwidth
- Device Drivers available for Linux, VxWorks®, and Windows®
- Rugged Air Cooled and Conduction Cooled versions
In terms of logic and DSP resources, the MM-7110 is the most powerful FPGA processing engine ever to be offered on the PMC form factor. By combining the Xilinx® VirtexTM-4 LX200 FPGA with the FPGA richest in DSP resources, the SX55, the MM-7110 addresses the most demanding signal processing requirements in a modular, flexible PMC form factor. | PMC Form Factor | Compliant with the IEEE P1386/P1386.1 CMC/PMC draft standard and the ANSI/VITA 20-2001 (R2005) standard for Conduction Cooled PMCs. | | Primary Device | Xilinx Virtex-4 LX200 -11 Industrial Grade | | Companion Device | Xilinx Virtex-4 SX55 -11 Industrial Grade | | Inter-FPGA Interconnect | Low Latency LVDS interface with up to 3GB/s of full duplex bandwidth | | PCI/PCI-X Bus Interface | In conventional PCI mode the bus interface operates at 32-bit or 64-bit data widths at 33MHz or 66MHz. In PCI-X mode the bus interface operates at a 64-bit data width at 66MHz or 133MHz. The PCI/PCI-X interface requires 3.3V signaling only and is compliant with the PCI-SIG PCI 2.2 bus specification. | | Address | 32 or 64-bit multiplexed with data on the PCI bus. | | Data In/Data Out | 32 or 64-bit, bi-directional (1-8 bytes controlled by byte enable signals C/BE[7..0]#). | | Modes of Operation | Read, Write, Burst Read, Burst Write, DMA Burst Read, DMA Burst Write. | | PCI Bus Memory Alignment | On 16MB window-size boundaries. | | PCI DMA Engine | Supports scatter/gather linked list operations. Mailbox feature generates a semaphore into host memory upon completion of a DMA transfer. | | Primary DDR2 Array | The multi-ported Primary DDR2 array can be configured with 512MB or 1GB of DDR2 memory with ECC. The default operating frequency is 200MHz but other frequencies can be supported upon request. | | ECC | An ECC engine on the Primary DDR2 array detects and corrects all single-bit errors, detects all double-bit errors, and some three and four bit errors within the same nibble. | | FPGA Platform Flash | The Virtex-4 LX200 and Virtex-4 SX55 are each independently equipped with FPGA platform Flash for additional bitstreams and independent reconfiguration. | | JTAG Ports | One JTAG port to the CPLD and one JTAG port to the FPGA Platform Flash. | | Status Indicators | Four user programmable LEDs. | | Power Rails | +3.3V only. Contact factory for specific power requirements. | | Mechanical Format | MM-7110 Physical Dimensions per the IEEE P1386/P1386.1 CMC/PMC draft standard and the ANSI/VITA 20-2001 (R2005) standard for Conduction Cooled PMCs:
Height: 143.75mm (5.65in) · Width: 74mm (2.91in) | | |
|
