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PMC-FPGA03 Virtex-II Pro PMC

User Programmable Virtex II Pro based FPGA PMC module

  • Xilinx XC2VP50 Virtex-II Pro™ FPGA
  • Multi-Gbps Serial I/O
  • Customizable Parallel Digital I/O
  • I/O Modules including LVDS and Camera Link
  • Multiple banks of QDR SRAM & DDR DRAM

The PMC-FPGA03 is a Xilinx XC2PV50 Virtex-II Pro based FPGA PMC module with high-speed digital I/O.

The PMC-FPGA03 is optimized for computationally intensive applications. The module is available in commercial, air-cooled and rugged, conduction cooled variants.

Overview
The PMC-FPPGA03 provides developers with access to a powerful Virtex-II Pro platform FPGA - the performance of which is enhanced by large external memory structures, making the PMC-FPGA03 ideal for a wide range of reconfigurable computing applications. Two main features of the Virtex-II Pro FPGA are the inclusion, as hard-IP, of embedded IBM PowerPC 405 RISC CPU cores and RocketIO Multi-Gigabit Transceivers (MGTs) for high speed serial communications.

Digital I/O
138 single-ended lines, directly connected to the FPGA, are routed to the front panel with a separate bank of 64 single-ended lines routed to the PMC user I/O connector. Each bank is independently configurable to 2.5V or 3.3V signaling, and each bank can be configured for differential signaling.

As an alternative to parallel digital I/O, the PMC-FPGA03 can be supplied as a build option with high-speed serial communications via the FPGA's embedded Gbps RocketIO transceivers. These interfaces can be used as low level 'data pipes' or configured (using appropriate IP) to one of many standard serial communications protocols such as serial RapidIO, Infiniband or Gigabit Ethernet. The embedded PowerPC 405 processors are ideally suited to higher-level control functions such as running the protocol stacks for these interfaces.

Memory
Two independent banks of 16-bit, 64Mbytes DDR SDRAM are connected directly to the FPGA. Clocked at 125MHz, the banks can be used completely independently (e.g. 500Mbytes/s 'ping-pong' memory operations) or collectively as a single 32-bit wide, 1Gbytes/s memory structure. This memory is accessible from the PCI bus and provides a large pool of memory to buffer DMA transfers and other large data block operations.

Software
Nearly all of the FPGA resource is left free for user applications. To aid FPGA configuration, example VHDL library code blocks are provided to show how the PMC-FPGA03 resources can be used. Flash programming utilities are also provided.

For the PMC host, a board support package is provided with C++ libraries for controlling DMA transfers and interrupts handling.

Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.


FPGA
Device Xilinx Virtex-II Pro XC2VP50
(call for other FPGA sizes)
Package FF1152
 
Memory
DDR SDRAM 2x 64Mbytes (125MHz)
SRAM 3x 2Mx18-bit (QDR-II) (125MHz)
FLASH 4Mbytes
FPGA Boot/Configuration
Programmable via PMC/PCI interface
 
PCI
Device QL5064
Compliance 32/64-bit PCI 2.2
33/66MHz
3.3/5V tolerant
Master/slave/DMA
Enhancements DMA, interrupt support
Bandwidth >500Mbytes/sec
 
Input/Output
Front Panel header behind front panel
(138-bit data/clocks plus power)
4x RocketIO channels
User I/O 64-bit data
 
I/O Adaptor Modules
ADC-MOD1 Dual 105 MSPS, 14-bit A/D
DAC-MOD1 Dual 210 MSPS, 14-bit D/A
LVDS-MOD3 32 differential pair LVDS
LVDS-MOD4 64 differential pair LVDS
CAML-MOD3 Base, Medium and Full mode Camera Link
RS485-MOD1 33 Channel RS485/422B Serial I/O
 
RocketIO
Front panel option 4 channels to 4 Tyco HSSDC 2 Infiniband 1X connectors
PMC user I/O option  
 
Standards
Conforms to IEEE 1386.1 (PMC module) specification
 
Environmental
Cooling Air/Convection
Temperature (Operating) 0°C to 50°C
Temperature (Storage) -40°C to 85°C
Humidity 0 to 95%
non-condensing
Vibration (Sine) N/A
Vibration (Random) N/A
Shock N/A
Conformal Coat No
For rugged build information please call.
 
Software Support
Toolschain Xilinx ISE 6.x XST
Utilities Flash and FPGA programming
(VxWorks and Windows NT/2000)
Example code DMA, interrupt handling etc.