CAML-MOD3

The CAML-MOD3 is a front panel mezzanine module designed to provide CameraLink I/O functionality to Curtiss-Wright's FPGA-based processing PMC modules. This module provides support for two digital cameras in Basic mode or one camera in Medium and Full mode. The CAML-MOD3 is aimed at embedded application development and is ideal for imaging and machine vision.

The CAML-MOD3 is designed to be used with:

Camera Link Module (CAML-MOD3)
Camera Link was developed by the Automated Imaging Association (AIA) as an extension of National Semiconductor's Channel Link technology. It forms a connectivity standard between digital cameras and frame grabbers in vision applications.The standard Camera Link cable provides for camera control signals, serial communication, and video data.

In the underlying technology, a single Channel Link interface is limited to 28 bits. This means that some cameras require several interfaces in order to transfer data as efficiently as possible. The Camera Link interface has three configurations:

Base - Single Channel Link interface
Medium - Two Channel Link interfaces
Full - Three Channel Link interfaces

With a throughput of up to 680 MB/s (into the FPGA) and integral camera control channels, Camera Link supports high resolution and/or high data rate color or monochrome cameras.

The CAML-MOD3 captures digital video from two cameras operating in base mode or one camera operating in medium or full mode for processing by the FPGA on the host PMC module. High end applications requiring significant parallel image processing computations, such as real-time filtering, feature recognition, target tracking, template matching, compression etc., are ideal for FPGA-based processing.

Software
The CAML-MOD3 is hosted by the PMC-FPGA03, PMC-FPGA05 or PMC-FPGA05 Development Kit which are supported under Windows XP, VxWorks and Linux. The CAML-MOD3 support package is additional to the BSP that accompanies our PMC modules and includes:

• VHDL library code blocks and software demonstrating how board resources can be used and Camera Link operations are controlled by the host FPGA
• Hardware and firmware/software manuals

Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.