HPE720 VPX 8640D & Dual Virtex-5

The HPE720 high performance hybrid processing engine coupling two Xilinx Virtex-5 FPGAs with a dual-core Freescale Power Architecture™ MPC8640D . With its combination of high performance CPU and dual FPGAs, this DSP product provides leading edge performance with flexible high-bandwidth I/O. This 6U VPX board is available in an air-cooled version with VxWorks or Linux board support packages. The HPE720 also supports the FusionIPC Inter-Processor Communication software stack for Distributed Multi-Processing (DMP) systems.

Processing
Architecturally, the HPE720 is a quad processor Digital Signal Processing engine for VPX/VPX-REDI (VITA 46/VITA 48). Two of these processor elements are combined into a single, highly integrated Freescale Power Architecture MPC8640D CPU. The other two processors are the two Xilinx Virtex-5 (LX220/330T or SX240T) FPGA devices. It is this CPU/FPGA combination that makes the HPE720 so powerful by leveraging the advantages of each technology. The FPGAs also maintain the VPX/VPX-REDI multi-gigabit serial communications. Both FPGAs are user programmable with tools, examples and utilities to simplify code development.

Memory
The MPC8640D PowerPC processor supports 1 GB of DDR II SDRAM. The HPE720 utilizes four independent banks of QDR II SRAM for each FPGA that are each 9MB in capacity. These banks of memory are each 36-bits wide. The HPE720 has two independent banks of 256MB DDR II SDRAM per FPGA. Each bank of DDR II is 32-bits wide. The HPE720 has up to 128MB of NOR FLASH.

Connectivity
Input/output is provided through a number of channels including gigabit Ethernet ports, FMC/XMC/PMC for a wide choice of I/O options, RS232 ports or VPX serial I/O for interboard communications. The HPE720 provides flexible front panel I/O with support for either two FPGA Mezzanine Card (FMC/VITA 57) site connected to the FPGAs or one FMC site and one XMC/PMC site. The XMC/PMC site supports PCI-X, and PCI Express, and Serial RapidIO (sRIO) options. Direct FPGA I/O is also provided through a parallel backplane-connected port for very high I/O speed. A sRIO fabric switch provides the quad Serial RapidIO x4 connectivity to the backplane.

Software
The HPE720 has Board Support Package (BSP) support for VxWorks 6.x and Linux 2.6.x with associated APIs for ease of customer development. Our FusionIPC, Inter-Processor Communication software stack for Distributed Multi-Processing (DMP) systems, and FusionXF FPGA Development Kit are supported on the HPE720.

Ruggedization
Designed from the ground up for rugged deployment, the HPE720 can be used in commercial, extended-temperature convection-cooled, and liquid-cooled (LFT) environments.

Priority Signature Support is available for this product.
 

FPGA
Device	Xilinx Virtex-5 LX220T, LX330T, and SX240T
No. of FPGAs	2
Memory (per FPGA)	4x 9MB QDRII SRAM (36-bit data paths at up to 250MHz) 2x -512MB DDR2 SDRAM (32-bit data paths at up to 267MHz) 16MB FLASH (for storing FPGA images only)
Connectivity	x8 GTP RocketIO per FPGA to backplane (P2 & P6) for LX330T/SX240T, x4 for LX220T x8 GTP RocketIO between FPGAs for LX330T/SX240T, x4 for LX220T x2 GTP to dedicated FMC site x2 GTP to FPGA0 from FMC1 (default) or FMC2 x2 GTP to FPGA1 from FMC2 (default) x4 sRIO to crossbar switch 38 Single Ended I/Os or 19 Differential Pairs to SCN
Configuration	JTAG, MPC864xD processor, SCN, off-board I/Os and on-board FLASH
PowerPC CPUs
Device	Freescale MPC8640D
CPU cores	2, e600
Speed	1.0 GHz
Memory	64KB L1 cache per core, 1MB L2 cache per core (inc. ECC), 512MB-1GB DDR2 per bank
FLASH	128MB, arranged as two 64MB banks or a single 128MB bank
NvSRAM	128KB on MPC8640D with RTC
Mezzanine Sites
FMC/VITA 57	Quad RocketIO x1 and 74 Differential Pairs for LX330T/SX240T, 68 for LX220T
XMC/VITA 42 & 46.9	J15 - PCIe x4/x8 or sRIO x4 J16 - 38 single-ended I/Os to SCN FPGA - Up to 16 differential pairs (P3/P4)
PMC/IEEE 1386.1	PCI (33/66MHz), PCI-X (66/133MHz), 32/64-bit, 3.3V signaling
Jn4/VITA 46.9	38 single-ended I/Os to the SCN FPGA or 18 Differential pairs and 2 Single Ended I/Os
Ethernet
Front Panel	Dual 1000BaseT (front panel RJ45)
Backplane	Dual 1000BaseX to P4 Connector
Device	Embedded within MPC8641D
Speed	10/100/1000Mbps
Serial RapidIO
Switch Device	Tundra TSI578 8-port sRIO switch
Connectivity	Both FPGAs, MPC8640D, optional to XMC, 4 connections to P1 fabric connector, all lanes at 3.125Gb/s
PCI Express
Connectivity	Optional to XMC (x4, x8), MPC8641D, Backplane (x8 on P2), all at 2.5Gb/s
Serial I/O
Device	DUART embedded within MPC8641D
Front Panel	Dual RS232
Backplane	Dual RS-232/422 to P4
Backplane
Compliance	VPX (VITA 46) and VPX REDI (VITA 48)
Connectivity P0 P1 P2 P3 P4 P5 P6	Power and SCN utility signals (I2C) 4 sRIO x4 to Switch 2 RocketIO x4 to FPGA1 and x8 PCIe (optional) 5 Differential pairs from J14, 8 Differential pairs from J16 and 38 Single Ended I/Os from SCN 8 Differential pairs from J16, 2 Gbit Ethernet SerDes Unused 2 RocketIO x4 to FPGA0
Processor Local Bus
Connectivity	32-bit wide connection from CPU to SCN
System Control Node
Device	Xilinx Virtex-5 LX70
Connectivity	32-bit wide connection to MPC8640D Dual I2C buses 38 single-ended connections to Jn4 38 single-ended connections to Jn6 Up to 38 single-ended connections to P3 38 single-ended connections or 19 differential pairs to FPGA0 and FPGA1
Software/HDL Code
Operating System	VxWorks 6.5, Linux 2.6.x (MPC8641D CPU)
Utilities	FLASH programming, diagnostics
HDL Code	FusionXF FPGA Development Kit, FusionIPC Development Kit and U-Boot
Standards
Compliance	VITA 20, 42.0, 42.2, 42.3, 46.0, 46.3, 46.9, 48 and IEEE 1386
Miscellaneous
Power	VPX 5V (3.3 W), +12V  (103.9W)
Cabling	Break-out cable with 4RS-232 connections, dual Gigabit Ethernet, JTAG & reset button (CABLE-1002)
Weight	A/C 2.61 lbs  1.18 Kg

 

 

 

Documents

HPE720 datasheet Technical Support fact sheet

Other Links

Ruggedization Levels Product Group Index ADC510 ADC511 ADC512 ADC513 ADX000 FusionXF FPGA Development Kit