PMC-FPGA03F Quad Virtex-II Pro PMC

The PMC-FPGA03F is an XC2VP50 Xilinx™ Virtex-II Pro FPGA based PMC supporting two or four fiber-optic I/O channels each of which connect to a RocketIO channel on the FPGA.

The PMC-FPGA03F complements the PMC-FPGA03 board, which has identical P14 user I/O connections and memory configurations. Together these two products provide options for front-panel high-speed serial communications (over copper or optical fibre) or parallel digital I/O using a common, firmware compatible architecture.

Communications
The PMC-FPGA03F is fitted with up to four duplex LC optical fiber connectors at the module's front panel. A range of transceivers are offered to provide hardware level support for a number of different data rate and transmission range requirements. The RocketIO (and hence fibre optic) signaling rate is set as a multiple (usually 20x) of the reference clock to the FPGA; so 2.0GHz signaling uses a high quality 100MHz reference. Signaling at or above this rate requires a -6 speed grade FPGA.

The default build option uses Stratos Lightwave 850nm VCSEL multimode optical fiber transceivers, which provide 1x/2x Fiber Channel data links through a duplex LC connector interface, to a distance of up to 500m.

Memory
Two independent banks of 16-bit, 64Mbytes DDR SDRAM are connected directly to the FPGA. Clocked at 125MHz, the banks can be used independently (e.g. 500Mbytes/s 'ping-pong' memory operations) or collectively as a single 32-bit wide, 1Gbytes/s memory structure. This memory is accessible from the PCI bus and provides a large pool of memory to buffer DMA transfers and other large data block operations.

Software/Firmware
Most of the FPGA resources are left free for user applications. To aid FPGA configuration, example VHDL library code blocks are provided to show how the PMC-FPGA03F resources can be used. This includes communications examples based around the Aurora protocol from Xilinx. Flash programming utilities are also provided.

For the PMC host, a board support package is provided with C++ libraries for controlling DMA transfers and interrupts handling.

Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.