DPIO2 Digital Parallel PMC

The DPIO2 is a PCI Mezzanine Card (PMC) designed for high-speed data acquisition and generation. It combines a Digital Parallel Input or Output on one end, and a 64-bit PCI bus master/slave interface with an advanced DMA controller on the other end, with a large FIFO in between. The PCI Interface chip provides a 64-bit PCI bus master/slave interface with a linked list DMA engine. The parallel interface is available through the front panel connector. The logical interface is based on the FPDP protocol. The electrical interface can be TTL (FPDP compliant), RS-422/485, PECL or LVDS, depending on what version of the DPIO2 is used.

The DPIO2 can be delivered with two FIFO sizes, either 32 or 128 Kwords. Different packing options are available: 1x32-bit, 2x16-bit or 3x10-bit can be selected, while 4x8-bit or 8x4-bit is available on request. That means that the front panel port can use less than 32-bits, but the data cycles on PCI will always will have the optimal width (32-bit or 64-bit). When using the DMA engine, both single and linked-list DMA is supported. For linked-list DMA, 64K of descriptors are set up in the onboard SSRAM (Synchronous Static RAM), eliminating PCI contention that would occur if the descriptors were stored in host memory. The DPIO2 is the second generation FPDP PMC (PCI Mezzanine Card) from us, now also supporting FPDP II in addition to original FPDP features. FPDP II is the new de-facto standard for high-speed parallel I/O. It is designed for digital data acquisition or generation at data rates up to 100 MSamples/sec or 400 MBytes/sec. Typically, the module is used to transfer huge amounts of raw sensor data between A/D or D/A converters and processors or memory/storage systems.

The rich set of features makes DPIO2 suitable for advanced parallel I/O such as digital video and variable length framed data. The DPIO2 is available with drivers for VxWorks, MC/OS and Windows 2000/NT. Driver source code is available for the purpose of porting it to other platforms.