Low Voltage Differential Signaling (LVDS) - PMC Front Panel Mezzanine Module
- 134 I/O lines routed as 64 differential pairs
- 152-pin front panel connector
- Mixed voltage signalling
- FPGA Firmware blocks supplied in VHDL for integration into user applications
- Windows, VxWorks and Linux host PMC support
The LVDS-MOD4 is a front panel mezzanine module designed to provide LVDS I/O functionality to Curtiss-Wright's FPGA-based processing PMC modules. This module provides 64 differential pairs to the front panel. The LVDS-MOD4 is aimed at embedded application development.
The LVDS-MOD4 is designed to be used with:
| - PMC-FPGA05 | A Virtex-5 LX110 FPGA based PMC |
| - PMC-FPGA05 Development Kit | A Virtex-5 LX110 FPGA based PCI board |
| - PMC-FPGA03 | A Virtex-II Pro XC2VP50 FPGA based PMC |
Low Voltage Differential Signaling Module (LVDS-MOD4)
The LVDS-MOD4 is a transition module designed to passively route all available I/O signals from the PMC-FPGA03 high density connector to a standard AMP/Tyco 767044-4, 152-pin front panel connector.
LVDS Signalling
134 I/O lines are routed as 64 length-matched differential pairs with 100 Ohm impedance traces, supporting the module's primary role of high-speed LVDS signaling. As standard, there are no termination resistors on the LVDS-MOD4 as the FPGA on the PMC module provides LVDS terminations at the receive buffers. However, there is a build option incorporating 100 Ohm resistors across each LVDS pair routed to the FPGA IO bank 1.
Single End Signalling
134 single ended signal lines are routed to the front panel connector. The PMC-FPGA03 provides signals to the LVDS-MOD4 module from two separate banks of the FPGA. The user can independently control the power rail for each of these two banks, allowing a mixture of 2.5V and 3.3V signaling to be used on both input and output signals. Table 1 shows the number of signals per bank.
Table 1
| FPGA Bank | No. IO lines | No. LVDS pairs |
| 0 | 69 | 33 |
| 1 | 69 | 33 |
5V Signalling
The LVDS-MOD4 provides a single, bi-directional 5V tolerant signal line.
Global Clock Inputs
The LVDS-MOD4 provides up to 8 (4 pairs) global clock inputs. Two pairs connect to bank 0 of the FPGA while the other two pairs connect to bank 1, though two pairs are routed by default: one clock pair per bank.
Software
The LVDS-MOD4 is hosted by the PMC-FPGA03, PMC-FPGA05 or PMC-FPGA05 Development Kit which are supported under Windows XP, VxWorks and Linux. The LVDS-MOD4 support package is additional to the BSP that accompanies our PMC modules and includes:
- VHDL library code blocks: demonstrating how board resources can be used and how
- Signaling operations are controlled by the host FPGA
- Hardware and firmware/software manuals
Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.
| Front Panel Signals |
| Number of LVDS Channels | 64 differential pairs |
| Connector | AMP/Tyco 767044-4 |
| Signaling | 2.5 / 3.3 V |
