Dual 125 MSPS, 14-bit ADC - PMC Front Panel Mezzanine Module
- Dual 14-bit, 125 MSPS Analog Input Channels
- FPGA Firmware blocks supplied in VHDL for integration into user applications
- Windows, VxWorks and Linux host PMC support
The ADC-MOD2 is a front panel mezzanine module designed to provide analog I/O functionality to Curtiss-Wright's Virtex-II Pro and Virtex-5 FPGA-based processing PMC modules. This module provides two channels of 125 MSPS, 14-bit analog to digital conversion. The ADC-MOD2 is aimed at embedded application development.
The ADC-MOD2 is designed to be used with:
| - PMC-FPGA05 | A Virtex-5 LX110 FPGA based PMC |
| - PMC-FPGA05 Development Kit | A Virtex-5 LX110 FPGA based PCI board |
| - PMC-FPGA03 | A Virtex II Pro XC2VP50 FPGA based PMC |
Analog Inputs
The dual channel 125 MSPS, 14-bit ADC-MOD2 has an onboard 125 MHz oscillator as well as provision for external clock sources. The sampling clock and trigger are made available to the host FPGA for complete application control. General purpose digital I/O signals are routed through to the front panel. These are also controlled by the host FPGA. These can be used for synchronizing multiple boards or providing alternative trigger mechanisms. Ideal applications in Software Defined Radio (SDR), radar and telecommunications.
Software
The ADC-MOD2 is hosted by the PMC-FPGA03, PMC-FPGA05 or PMC-FPGA05 Development Kit which are supported under Windows XP, VxWorks and Linux. The ADC-MOD2 support package is additional to the BSP that accompanies our PMC modules and includes:
- VHDL library code blocks: demonstrating how board resources can be used and how ADC operations are controlled by the host FPGA
- Hardware and firmware/software manuals
Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.
** The ADC-MOD2 replaces the ADC-MOD1.
| Front Panel Analog Signal Input |
| Number of Channels | 2 |
| Connectors | AC coupled, frontpanel MMCX connector |
| Full Scale Input | +10 dBm (2V pk-pk) into 50 ohms |
| SNR | 68dB |
| SFDR | 82dB |
| A/D Converter |
| Quantity | 1 |
| Type | Linear Technology LTC2285 |
| Sampling Rate | 125MSPS |
| Resolution | 14 bits |
| Bandwidth | 100kHz to 110MHz full power bandwidth |
| External Clock Input |
| Connector | Front Panel MMCX |
| Input Level | 200 - 1000 mV pk-pk, sine or squarewave |
| Input Impedance | 50 Ohms, AC coupled LVPECL |
| Clock Selection | Controlled by FPGA |
| Trigger |
| Single-ended, 50 Ohm, DC coupled |