ADC510 Dual Channel Analog Input FMC

The ADC510 enables integration of dual channels of analog input into embedded computing systems. The innovative design of the ADC510, based on the emerging VITA 57 standard, makes it easier for developers to integrate FPGAs and analog input into their embedded system designs. Typical DSP applications for this module include Signal Intelligence (SIGINT), Electronic Counter Measures (ECM), and Radar.

The ADC510 utilizes two Texas Instruments ADS5463/ADS54RF63 ADC devices with each device supporting a sampling rate up to 550MSPS and providing 12-bits of digital output. The ADC device interfaces are routed to the FMC connector to enable an FPGA on a baseboard to directly control and receive data. The high bandwidth connectivity of the FMC interface ensures that data can be transferred to the FPGA without compromising the throughput. The analog inputs are 50 Ohm AC coupled and connect through the front panel using MMCX connectors.

Clock and Trigger Signals
A number of clock input options are available using onboard or external sources. The onboard source is selectable by the host FPGA and provides sample rates of 300, 320, 400 and 500MSPS. External LVPECL compatible trigger input and outputs are provided and linked to the FPGA host. These signals can be used for a variety of purposes including triggering, gating, and multi-board synchronization with the appropriate HDL application code.

FMC
The FMC/VITA 57 (draft) specification allows I/O devices that reside on an industry standard mezzanine card to be attached to, and directly controlled by, FPGAs that reside on a baseboard. The benefits are increased performance, higher bandwidth, reduced latency, lower cost and less complexity. To maximize data throughput and minimize latency, the FMC connector has many pins that support high-speed signals for moving data between the FMC and an FPGA on the baseboard.

ADC510 Hosts
The ADC510 can be fitted to our hosts including the FPE650, a quad Xilinx^® Virtex^®-5 VPX Processor board with dual FMC sites. The combination of the ADC510 and a FPGA provides a high quality high performance solution in a single VPX/VPX-REDI slot.

The ADC510 is supported by Curtiss-Wright's XF suite which includes software APIs for remote hosts and HDL examples.

Analog Input
Number of Channels	2, single-ended
Sampling Frequency	Up to 550MSPS
Full Scale Input Voltage	2V2 pk-pk
Device	2x TI ADS5463/ADS54RF63
Input Bandwidth (3dB)	>1.7GHz
Input Impedance	50 Ohm, AC coupled
SNR (device)	65 dBFS
SFDR (device)	73 dBc
ENOB (device)	10.1 bits at 250MHz
Clock & Trigger Inputs
Clock Input Connector	Front panel MMCX
Clock Input	50 Ohm, AC coupled LVPECL
Clock Input Frequency	Sample rate is half input clock frequency (i.e. 1GHz for 500MSPS)
Internal clock	Selectable from - 600MHz: 300MSPS - 640MHz: 320MSPS - 800MHz: 400MSPS - 1000MHz: 500MSPS
Trigger Input/Output	Single-ended, 50 Ohm, LVPECL buffered to host FPGA
Misc.
LEDs	2x yellow (host FPGA controlled)
Digital I/O	4 differential pairs
Software/HDL Code
Host HDL Code	Analog input hosted by our XF suite on FPE650 6U quad FPGA VPX (contact Sales for other hosts)
Environmental
Ruggedization levels	Air-cooled, air-cooled rugged and conduction-cooled

Documents

ADC510 datasheet Analog I/O fact sheet

Other Links

Ruggedization Levels Product Group Index FPE320 FPE650 HPE720 FusionXF FPGA Development Kit