User Programmable Virtex-5 SX95T FPGA XMC/PMC module with plug-in I/O Adapter Modules
- Xilinx Virtex-5 SX95T (default), LX155T or FX100T FPGA
- Customizable digital I/O
- Two banks of 9MB QDR2 SRAM for DSP
- Two banks of 128MB DDR2 SDRAM for large buffers
- PCIe/PCI-X interface
- Windows, VxWorks and Linux support
- Air and Conduction cooled variants
The XMC-FPGA05D is a high density I/O PMC/XMC module, supported by a user programmable Virtex-5 FPGA. The board may be used as a PMC with a 64-bit, 133MHz PCI-X interface to the host or as an XMC module supporting a x8 PCI Express interface to the host.
Xilinx Virtex-5 FPGA
The default Virtex-5 FPGA fitted is the SX95T, speed grade 2 (contact factory for alternative FPGA variants).
The FPGA may be configured from FLASH or configuration SRAM. As the SRAM is volatile, no configuration data is left on the board after a power cycle – an important factor in some secure applications. SRAM also has the added benefit of faster FPGA reconfiguration times.
Multiple configuration images may be stored in the flash, which is indexed to allow user selection of which image to use.
Front Panel Digital I/O
There are 138 signals routed to a 180-way connector near the front panel. These lines are routed so that they may be used as single-ended signals or differential pairs. The FPGA I/O signals are banked, with four banks being used at the front panel connector. Each bank is independently configurable to 2.5V or 3.3V signaling.
Developers can select from a range of existing modules, which includes support for LVDS, RS485 and Camera Link. Alternatively, users may create custom modules tailored to their application from the complete specifications within the documentation supplied with the board.
Host Digital I/O
In a PMC configuration, the PMC user I/O connector, P14, is available to support host I/O and can be configured as 32 LVDS pairs, 20 LVDS pairs plus 24 single-ended lines or as 64 single ended lines.
Memory
By default, two banks of 9 Mbytes QDR II SRAM support DSP functions in the Virtex-5 and are independently connected to the FPGA with an 18-bit interface, allowing great flexibility in how they are used.
Two independent banks of 128 Mbytes per second DDR2 SDRAM, are directly connected to the FPGA. With a 16-bit interface, each bank can be used independently or as a single 32-bit wide memory structure. This memory provides a large pool of memory to buffer DMA transfers and other large data block operations.
Software/HDL code
The XMC-FPGA05D is supported by Curtiss-Wright’s FusionXF development kit under Windows, VxWorks and Linux. The package includes:
- VHDL library code blocks (demonstrating how board resources can be used)
- Driver framework that simplifies the addition or removal of IP functionality
- API with C support libraries
- Example code
- FLASH/SRAM programming and board debug utilities
- Hardware, firmware development and software manuals
Development of VHDL code for the FPGA requires synthesis tools such as Xilinx ISE Foundation.
