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ADC512 Dual Channel Analog Input FMCDual Channel 3 GSPS 8-bit ADC FPGA Mezzanine Card (FMC)
________________________________________ The ADC512 provides system developers with ability to directly connect analog input with FPGA based embedded processing nodes. As the ADC512 is part of a range of modular I/O solutions conforming to the VITA 57 FMC standard, developers can change I/O formats by changing relatively low cost modules while the more expensive host processing cards remain the same. This allows developers to reuse host firmware and software elements from previous projects thus reducing cost, development times and risk. Typical DSP applications for this module include Signal Intelligence (SIGINT), Electronic Counter Measures (ECM), and Radar. The analog inputs to the FMC feed through front panel MMCX connectors. Input impedance is 50 Ohm, AC coupled. The ADC512 uses two National Semiconductor ADC083000 analog to digital converters. Each device supports a sampling rate up to 3 GSPS with 8-bit resolution. The digital outputs of the ADCs are routed as LVDS signals to the high-bandwidth FMC connector, through which the baseboard FPGA receives the data and controls the data flow. LVPECL compatible trigger input and output is directly linked to the FPGA host. Trigger signals can be used for a variety of purposes including triggering, gating, and multi-board synchronization when using the appropriate HDL application code. FMC An FMC module uses either a Low Pin Count (LPC) connector with 160 pins or a High Pin Count (HPC) connector with 400 pins (like the ADC512). The connector supports single-ended and differential signaling up to 2 Gbps and Multi-Gigabit Transceivers (MGTs) up to 10 Gbps. These connections are directly to the FPGA, removing bridge latencies and maximizing data throughput. ADC512 Hosts The ADC512 is supported by Curtiss-Wright's XF suite which includes software APIs for remote hosts and HDL examples.
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