VPF1 Dual 744x & Virtex-II Pro

The VPF1 is a 6U VME digital signal processor supporting VXS (VITA 41) backplane switch fabric communications (using VXS P0 connector). The VPF1 comprises four processor nodes; two based on the 1GHz PowerPC 7447A/7448 CPUs and two nodes on based Xilinx™ Virtex-II Pro FPGAs. All the processor nodes have a distributed memory architecture and each node has multiple inter-node communications channels. This communications fabric binds together both the local processor elements and those on separate boards for seamlessly scalable processing solutions.

PowerPC
The VPF1 provides each of the 1GHz PowerPC 7447A/7448 nodes with either 256 or 512Mbytes of DDR SDRAM (with ECC). Each node is coupled via a Marvell MV64360 bridge which provides two Gigabit Ethernet channels, RS422 and RS232 ports as well as a PCI and PCI-X interfaces. The SDRAM is implemented with 72-bit datapaths and clocked at 125MHz for an effective data rate of up to 2Gbytes/sec. 32 or 64Mbytes FLASH memory is available per node.

Ethernet + RS422 & RS232 Interfaces
Two off-board Gigabit Ethernet interfaces are provided, one from each PowerPC processor node. A further Gigabit Ethernet port connects the two PowerPC nodes together. The off-board interfaces are routed to the VME P2 connector, though a build option provides front panel connectors for non conduction-cooled variants too. One RS422 interface with RTS/CTS handshaking and one RS232 port is provided per PowerPC node. These ports are made available to the VME P2 connector (optionally via a VME P2 adapter/breakout module).

Virtex-II Pro FPGAs
The VPF1's FPGA nodes are based around Xilinx XC2VP70 Virtex-II Pro devices. Each node is provided with eight 2.0/3.125Gbps SERDES transceiver pairs, a 64-bit/125MHz parallel bus to it's adjacent PowerPC bridge, four banks of 2M x 18-bit QDR SRAMs and two banks of 64Mbytes DDR SDRAM (both memory types are directly linked to the FPGA for maximum flexibility) and a JTAG port.

Each FPGA's configuration file is supplied by the attached PowerPC processor and is stored in the PowerPC CPU's FLASH. The development tools facilitate programming the FPGA in both development and run-time environments. JTAG can also be used for FPGA configuration during development. An onboard battery build option is available so that encrypted keys can be stored for secure FPGA configurations.

Gigabit Serial Communication Channels
The Virtex-II Pro FPGAs feature 2.0/3.125Gbps RocketIO™ transceivers channels. Four channels link the two FPGA nodes and four channels from each FPGA are available for off-board communications. Groups of RocketIOs from a single device can be 'bonded' together to synthesize higher bandwidth data links.

Software
The BSP library provides integration support for using the VPF1 from within a host application. It is a C++ library supporting general hardware access and the implementation of high-speed DMA routines. Full source code for the libraries is supplied. Example programs using these library routines are included to perform such tasks as setting up various DMAs to and from the board and interrupt handling.

The host services provided by the libraries usually requires the support of an operating system dependent device driver. Drivers for VxWorks and Linux operating systems are supported.

Host utilities are provided to give the user a graphical user interface with a complete view of the board hardware (registers, memory, etc.). Other utilities allow for system evaluation and functional testing, as well as configuring the FPGA from the host and loading the FLASH.

Note:
1. Please consult Curtiss-Wright for 7447A (1,000MHz) and 7448 (1,250MHz) devise availability.