3CPF1 3U PowerPC 744X & Virtex-II FPGA

The Phoenix 3CPF1 is a modular signal and data processing engine harnessing the combined power of PowerPC CPUs, large Xilinx™ FPGAs and high-bandwidth multichannel serial communication fabric. This creates a balanced and scalable compute platform for radar, sonar, electronic warfare and real-time imaging applications.

A complete rugged and systems based roadmap, means that the Phoenix 3CPF1 can be used as a common building block to a range of systems and results in accelerated development cycles and fast time-to-market.

PowerPC
The PowerPC processor node is a fully self-contained processor complete with memory, bus and network interfaces. The 1GHz PowerPC 7447A comes with 256 or 512Mbytes of DDR SDRAM (with ECC) and is globally accessible. The memory is coupled to the PowerPC CPU via a Marvell MV64360 bridge which also provides two Gigabit Ethernet channels, RS422s and RS232 ports as well as a PCI interfaces. The SDRAM is implemented with 72-bit datapaths and clocked at 125MHz for an effective data rate of up to 2Gbytes/sec. 64Mbytes FLASH memory is available.

Ethernet + RS422 & RS232 Interfaces
Two off-board Gigabit Ethernet interfaces are provided from the PowerPC processor node. The off-board interfaces are routed to the backplane, though a build option allows routing to RJ45 front panel connectors for non conduction-cooled variants. One RS422 interface with RTS/CTS handshaking and one RS232 port are also provided. These ports are also made available to a backplane connector. Both ports are fully available for user applications and can be used for a serial console as required by VxWorks for boot configuration.

Virtex-II Pro FPGAs
The Phoenix 3CPF1's FPGA node is based around the Xilinx XC2VP70 Virtex-II Pro device. The node is provided with eight 2.0/3.125Gbps SERDES transceiver pairs, a 64-bit/125MHz parallel bus to it's adjacent PowerPC bridge, four banks of 2M x 18-bit QDR SRAMs and two banks of 64/128Mbytes DDR SDRAM (both memory types are directly linked to the FPGA for maximum flexibility) and a JTAG port.

The FPGA's configuration file is supplied by the attached PowerPC processor and is stored in the PowerPC CPU's FLASH. Our development tools facilitate programming the FPGA in both development and run-time environments. JTAG can also be used for FPGA configuration during development. An onboard battery build option is available so that encrypted keys can be stored for secure FPGA configurations.

Gigabit Serial Communication Channels
The Virtex-II Pro FPGA features 2.0/3.125Gbps RocketIO transceivers channels. Eight channels from the FPGA are available for off-board communications. Groups of RocketIOs from a single device can be 'bonded' together to synthesize higher bandwidth data links.

Software
The BSP library provides integration support for using the Phoenix 3CPF1 from within a host application. It is a C++ library supporting general hardware access and the implementation of high-speed DMA routines. Full source code for the libraries is supplied. Example programs using these library routines are included to perform such tasks as setting up various DMAs to and from the board and interrupt handling.

The host services provided by the libraries usually requires the support of an operating system dependent device driver. Drivers for VxWorks and Linux operating systems will be supported.

Host utilities are provided to give the user a graphical user interface with a complete view of the board hardware (registers, memory, etc.). Other utilities allow for system evaluation and functional testing, as well as configuring the FPGA from the host and loading the FLASH.