The FPE650 is a quad FPGA processor card which combines high performance and high bandwidth I/O in a flexible format. Provided in a 6U VPX format, the FPE650 has a large number of multi-Gigabit/sec serial and parallel data links to the backplane as well as FMC (VITA 57) mezzanine sites for direct I/O to the FPGAs without introducing data bottlenecks. Each of the FPGAs include multiple banks of memory to help maximize the capabilities of the Xilinx Virtex-5 SX95T FPGAs. The FPE650 is designed for the most demanding digital signal processing applications such as Electronic Counter Measures, Signal Intelligence and Electro-Optics.
Xilinx Virtex-5 FPGA Nodes
The four SX95T FPGAs are closely coupled for multiple banks of QDR2 SRAM and DDR2 SDRAM (depending on FPGA site) for increased system performance. The FPGAs are inter-connected through a network of x4 RocketIO links and parallel connections for high bandwidth, low latency data communications. There are dedicated high speed links that connect to the front panel FMC sites and VPX backplane connections.
FMC Sites
Two FPGAs are connected to an FPGA Mezzanine Card (FMC) site. FMC is defined by the VITA 57 specification as a mezzanine format designed to take advantage of FPGA based I/O - high bandwidth, reduced latency, simplified design and lower cost. FMCs do not require CPU busses such as PCI and consequently all control and flexibility is embodied within the FPGA directly. The FPE650 provides 68 differential parallel FPGA links to each site, a x4 full duplex RocketIO link and an Ethernet port. A zero latency cross bar switch is used to determine how the FMC x4 RocketIO link is used thereby providing a flexible solution.
VPX/VPX-REDI
ANSI/VITA 46.0-2007 provides a large number of high speed serial data links and ideal for FPGA solutions. Dual x4 links to all FPGAs are made available to the backplane for high bandwidth communications to the VPX backplane. There are additional x4 links, via a cross bar switch on the FPE650, and parallel backplane connections to two FPGAs increase I/O and system bandwidth further.
Commercial air-cooled, rugged air-cooled and conduction-cooled variants are also available compliant to the VPX-REDI mechanical format. The default board pitch is 1".
Configuration Control Processor (CCP)
Embedded within the FPE650 is a CCP. This has two roles: to configure the FPGAs via FLASH or SDRAM and to setup up the cross bar switch. The CCP is accessed by an HTML browser attached to front or backplane Ethernet connections.
Software/HDL Support
The FPE650 is a pure FPGA board and intended to be used alongside a CPU system controller. Sophisticated HDL examples are provided such as DMA driven memory interfaces, FMC sites and network connected FPGAs. JTAG headers are provided for application development using ChipScope tools. Support is provided for the Xilinx ISE toolchain.
Digital Receiver
The combination of processor performance, high bandwidth, interchangeable FMC module for analog I/O and Curtiss-Wright FPGA IP make the FPE650 an ideal digital receiver platform. Ideal applications include Signal Intelligence (SigInt), Software Defined Radio and Radar applications.
| FPGA Node 1 & 3 |
| Devices | Xilinx Virtex-5 SX95T (speed grade 2) |
| DDR SDRAM | 2 banks of 128M x 16-bit and
2 banks of 128M x 24-bit |
| QDR SRAM | 2 banks x 4M x 18-bit |
| User FLASH | 128 Mbytes per FPGA |
| Parallel I/O | 20 differential pairs per FPGA (1 & 3 only) to VPX P3/P6 connector |
| FPGA Node 0 & 2 |
| Devices | Xilinx Virtex-5 SX95T (speed grade 2) |
| DDR SDRAM | N/A |
| QDR SRAM | 4 banks x 4M x 18-bit |
| Parallel I/O | 102 single-ended signals between FPGA 0-1 and FPGA 2-3 |
| FMC Sites |
| FMC site 1 | FPGA Node 1 Host
- 68 differential pairs
- x4 Multi-Gbps serial port
- Ethernet (SERDES) |
| FMC site 2 | FPGA Node 2 Host
- 68 differential pairs
- x4 Multi-Gbps serial port
- Ethernet (SERDES) |
| Configuration and System Monitoring |
| FLASH | 128 Mbytes (FPGA configuration) |
| Control port | Ethernet (FMC site or backplane)
HTML browser interface |
| VPX/VPX-REDI |
| Compliance | ANSI/VITA 46.0-2007
VITA 48.0 |
| Board Pitch | 1" (contact CWCEC for 0.8" variants) |
| Power Supplies | 12V, 5V, 3V3, 3V3 Aux, VBAT (used for maintaining FPGA encryption keys) |
| Environmental Builds | Commercial air-cooled, rugged air-cooled and rugged conduction-cooled |
| Miscellaneous |
| LEDs (yellow) | - User programmable LEDs (two per FPGA) |
| LEDs (red) | - FPGA not configured (one per FPGA)
- Configuration controller not configured
- Fault detection |
| Software/HDL |
| Host Drivers for remote host processors | Windows, VxWorks, Linux |
| HTML browser | Embedded processor HTML interface for FPGA configuration, crossbar switch configuration, temperature monitors, power supply sensors and FLASH programming |
| Software/HDL examples | Memory interfaces, data streaming library |
Quad Xilinx Virtex-5 FPGA VPX Processor Board with Dual FMC Sites