FPE320 VPX Virtex-5 FPGA

The FPE320 is a 3U VPX FPGA processor board that incorporates the largest Xilinx Virtex-5 FPGAs available with an FMC mezzanine site. Providing a large amount of resources in a small, rugged form factor, the FPE320 is the ideal FPGA platform for 3U systems that need to acquire analog and other high-speed I/O or need a large FPGA processor.

FPGAs have been adopted for their incredible processing capability, as well as their ability to fit this capability in reduced size, weight, and power (SWaP) constraints. The inherent parallelism of FPGAs makes them well suited for a variety of image and signal processing applications that have historically been satisfied with a large array of general purpose processors. When complex algorithms are partitioned into FPGAs, users can see increases in performance that can lead to a dramatic reduction in slot count and system cost, which are at a premium in 3U systems.

As system platforms have shrunk, many designers have considered 3U boards. 3U VPX has provided an ideal platform for high-speed serial interconnects (HSSI) such as PCI Express (PCIe), Aurora, and Serial RapidIO (sRIO) to the backplane, but board constraints have limited the use of large FPGAs with I/O. With the advent of the FMC mezzanine site, or FPGA mezzanine site, large FPGAs can be used in 3U systems because the I/O space requirements are minimized. FMC is a standard conceived to allow designers to take advantage of advances in the latest I/O (ADC's, DAC's, etc.) and couples this I/O directly to FPGAs. This allows users to take advantage of low latency and high bandwidth that FPGAs support, while its flexibility eases design for multiple I/Os and allows for dissipating heat more effectively. The FPE320 combines the I/O resources of the FMC with the backplane connectivity of 3U VPX to maximize the effectiveness of these large FPGA resources.

The FPE320 is supported by the FusionXF Development Kit, which provides infrastructure and support for HDL development, software, and multi-processing applications, including PCIe, Aurora and Serial RapidIO. VxWorks™ and Linux are supported operating systems for the processors that interact with the FPE320.

Xilinx Virtex-5 FPGA
At the heart of the FPE320's processing is a Xilinx Virtex-5 FF1738 package FPGA, the largest FPGA in the Virtex-5 family. FPGAs provide parallel processing capabilities that can be used to reduce processor count and system size. Operations such as FFTs, FIR filters and other fixed-point and/or repetitive processing tasks are highly suited for placement inside FPGAs. By providing a large FPGA node, processing tasks can tackle input from the FMC mezzanine site, backplane I/O or simply function as an adjunct processing resource to the general purpose processor in the system.

The FPE320 supports Xilinx Virtex-5 LXT, SXT, and FXT devices. Using the LXT for logic-intensive applications, the SXT for DSP applications, and the FXT for all-around performance, developers can tailor their hardware resources to match their algorithm needs. 

In the LXT family, we support the LX330T. LX220T, and LX155T devices. With over 330,000 logic cells, the LXT family gives FPGA designers the most amount of space to program their algorithm. In the SXT family, the SX240T device is supported. With 1,056 DSP slices and over 240,000 logic cells, the SXT device is ideal for A/D projects where the DSP48E slices can be used to maximum benefit. In the FXT package, we support the FX200T and FX130T, incorporating the best of the other families in one device. The FXTs provide ample Block RAM and two embedded PowerPCs™.

Memory
The memory resources on each FPGA node of the FPE320 gives users the ability to process and store data sets for the most demanding applications. Each FPGA node has both DDR2 and QDR-II SRAM available. The DDR2 is organized into two banks, with each bank providing a x32 bus width using two x16 devices. Up to 512MB of memory is available from each DDR2 bank, providing a large amount of storage space for data sets. Complementing the DDR2 for more processing intensive tasks are two independent banks of QDR-II SRAM banks. The banks each have a x36 bus width, and provide immense bandwidth as they are quad data rate. The QDR-II banks do not need to track addressing because they are SRAMs, shortening development time for the user. Each bank is 9MB, for a total of 18MB available from each FPGA. 12MB of FLASH is available for storing bitstreams, although they can also be loaded through the System Controller Node (SCN).

FPGA I/O
The FPGA node on the FPE320 has a tremendous amount of  I/O resources for connecting to other parts of the system. In terms of RocketIO™ high-speed serial links, the FPGA compute node utilizes up to 20 RocketIOs depending on which package is used. For the larger devices, such as LX330T, SX240T and FX200T, 20 links are used. These links are divided between I/O to FMC and to the backplane. Parallel I/O is also used, with up to 164 lines routed to the dedicated FMC site, and 38 single-ended I/Os or 18 differential pairs and 2 single-ended I/Os routed to the SCN.

System Control & Chassis Management
The on-board SCN controls chassis management, temperature monitoring, JTAG, bitstream encryption, and routing of single ended I/Os.

Mezzanine Site
The FPE320 includes a versatile set of I/O options through a FPGA Mezzanine Card (FMC) mezzanine site (VITA 57). FMCs provides fl exibility for the latest I/O such as A/D converters, SerialFPDP (sFPDP), LVDS, and others, and can also be designed by customers by following the VITA 57 standard.

FusionXF FPGA Development Kit
The FPE320 uses the FusionXF FPGA Development Kit to speed HDL development and to communicate with processors and other FPGAs in a system. FusionXF provides FPGA Hardware Development Logic (HDL) functions, application APIs, drivers, and utilities to simplify the task of integrating FPGAs into an embedded real-time DSP system design. It aids customers in the development of their FPGA algorithms and logic for our customer- programmable FPGA products by providing all the building blocks to build a fully functional FPGA design to which a customer can integrate their FPGA logic and algorithms. FusionXF also provides mechanisms for communication between FPGAs as well as communication between FPGAs and processors. It includes example designs that show how to implement common FPGA functions such as control registers, DMA engines, interrupts, etc. and how to control these functions and communicate with them from software.

FPGA
Device	Xilinx Virtex-5 LX155T, LX220T, LX330T, SX240T, FX130T & FX200T
No. of FPGAs	1
Memory (per FPGA)	2x 9MB QDRII SRAM (36-bit data paths at up to 250MHz) 2x 256-512MB DDR2 SDRAM (32-bit data paths at up to 267MHz) 12MB FLASH (for storing FPGA images only)
Connectivity	32 Single Ended I/Os or 16 Differential Pairs to P1 1 RS-232 with HandShake (CTS/RTS), Dual RS-232, or 2 Single Ended I/Os to P1 38 Single Ended I/Os or 18 Differential Pairs and 2 Single Ended to the SCN
System Control Node
Device	Xilinx Virtex-5 LX30
Memory	128MB DDR2 SDRAM (16-bit wide) 4MB FLASH (for storing FPGA images only)
Connectivity	32 Single Ended I/Os or 16 Differential Pairs to P2 8 Dedicated Single Ended I/Os to P2 38 Single Ended I/Os or 18 Differential Pairs and 2 Single Ended to the FPGA processor Dual I2C buses to P0
Configuration	JTAG, SCN, off-board I/Os and on-board FLASH
Mezzanine Site	FMC/VITA 57 Quad RocketIO x1, 73 Differential Pairs & 2 Single Ended for LX330T/SX240T/FX200T 68 Differential Pairs and 8 Single Ended for LX220T/FX130T
PCI Express
Connectivity	Default configuration is PCIe x8 to P1 & RocketIO x8 to P2
Compliance	VPX (VITA 46) & VPX REDI (VITA 48)
Connectivity
P0	Power, JTAG & SCN utility signals (I2C)
P1	2 x4 GTP RocketIOs 32 Single Ended I/Os or 16 Differential Pairs 1 RS-232 with HandShake (CTS/RTS), Dual RS-232, or 2 Single Ended I/Os
P2	2 x4 GTP RocketIOs to backplane 32 Single Ended I/Os or 16 Differential Pairs 8 Dedicated Single Ended I/Os
Software/HDL Code
Operating System	VxWorks 6.5, Linux 2.6.x (run on adjoining processor, not FPE320)
Utilities	FLASH programming, diagnostics
HDL Code	FusionXF FPGA Development Kit
Standards
Compliance	VITA 46.0, 46.4, 48
Board Pitch	.8"
Miscellaneous
Power	VPX 3.3V (TBA W), 5V (TBA W), +12V (TBA W), -12V (TBA W)
Cabling	JTAG Cable and Adapter (p/n JTAG-1001)
Weight	TBA