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MM-1650 VPX Dual Virtex-4
VPX Serial RapidIO Intelligent IO Carrier with Dual User Programmable Virtex-4 LX160 FPGAs
- 2x CoSine 2VP100 System-on-Chips
- 2x Xilinx Virtex-4 LX160 CoSine Companion Devices
- 2x XMC/PMC sites
- 14 independent memory arrays with total bandwidth over 40GBps
- 4x embedded PowerPC processors
- Complete Serial RapidIO x4 connectivity
- 6U VITA-46 (VPX) form factor
- Rugged air-cooled and conduction-cooled variants
The MM-1650 combines the industry's most powerful System-on-Chip, CoSine™, with the application optimized architecture of an Othello® VME carrier.
Mezzanine Sites Mezzanine sites on the MM-1650 can support either PMCs or XMCs. Configured for PMC support, each PCI bus can operate in 32-bit or 64-bit PCI 2.3 mode at up to 66MHz or in 64-bit PCI-X mode at up to 133MHz. Configured for XMCs, the sites can support the Aurora™ protocol with four MGTs or Serial RapidIO x4.
Backplane Connectivity In addition to having a VME320 2eSST interface, the MM-1650 is the first VME board to include complete on-board Serial RapidIO switch fabric connectivity, with four independent Serial RapidIO ports to the VITA 46 P1 MGT backplane connector per the VITA 46.3 draft standard.
LX160 and VirtexTM-4 Logic Slices The MM-1650 is the first VME board to include the Virtex-4 LX series of FPGAs from Xilinx®. The LX device is notable in the large amount of FPGA slices that it provides for logic intensive implementations.
It can sometimes be difficult to predict logic resource utilization requirements in advance of RTL implementation. The LX family addresses this concern by offering massive logic densities. In the Xilinx Virtex-4 portfolio, the LX160 is second in size only to the LX200. It offers over 67,000 FPGA slices for logic-centric applications requiring maximum gate count.
While using RTL abstraction tools such as The MathWork's Simulink and Xilinx System Generator can reduce FPGA development time, resulting compiled VHDL can be verbose and require many more slices than might otherwise be required from hand coded state machines. The LX160 counters this concern by providing a large platform that provides the equivalent of approximately 15 million ASIC gates.
CoSine Compute Nodes The MM-1650 contains two independent CoSine Compute Nodes (CCNs). A single CCN is comprised of a CoSine Primary Device (VirtexTM-II Pro 2VP100), a CoSine Companion Device (Virtex-4 LX160) and the following:
- Two embedded PowerPC 405GP processors
- One multi-ported primary DDR array, up to 1GB, for seamless bus translation between the mezzanine port and crossbar port to the backplane
- Two dedicated 128MB DDR arrays local to each PowerPC processor
- Four independent 9MB QDR II SRAM arrays local to the LX160 for FPGA processing operations
- FPGA Platform Flash
Aggregate memory bandwidth exceeds 20GB/s per CCN, providing a total of over 40GB/s on the MM-1650.
PowerPC Processors and Infrastructure Each of the two embedded PowerPCs in each 2VP100 is a fully functional computer, each with its own DDR array, programmable Flash, UART, and shared Ethernet. Processors can host device drivers, perform message passing, service interrupts, or execute floating point operations. Each processor includes a complete BSP with all internal SoC device drivers fully integrated so customers can download application files "out of the box".
Reconfigurable Processing Each of the LX160s have additional FPGA platform Flash to store multiple bitstreams. Because the principal System-on-Chip functionality is largely contained in the 2VP100 CoSine Primary Device, the MM-1650 is optimally designed for reconfigurable processing. This approach enables the LX160 CoSine Companion Devices, which contain User Programmable Logic, to be reconfigured by the 2VP100 CoSine Primary Devices without the 2VP100s needing to reconfigure themselves.
Temperature Sensing The MM-1650 contains a CPLD that monitors the temperatures of the CoSine Primary Devices, CoSine Companion Devices, and primary circuit board to ensure proper operation. Status updates can be received by the CoSine PowerPC processors that can then make intelligent decisions, display status to user programmable LEDs, or communicate information over its Ethernet link to remote destinations.
Debug Ports Debug ports include four RS-232 UART consoles, one board/system push button reset switch, and two processor JTAG debug ports. Debug ports are available out the front panel or backplane via P0.
Ruggedized Options The MM-1650DR is a rugged, extended temperature air cooled board with an operating temperature of -40°C to +71°C. The MM-1650DTE is a rugged conduction cooled board with an operating temperature of -40°C to +85°C with cabling out the front panel. The MM-1650DR and MM-1650DTE were designed for optimal heat dissipation and deployment in environments that undergo severe shock and vibration.
* Note: while the MM-1650 is designed to meet these environmental requirements, formal qualification testing has not been performed to these levels. Please contact your local sales representative to discuss your program specific requirements.
| Mezzanine Sites |
Two independent mezzanine sites each support PMCs or XMCs. The PMC sites are provided with 3.3V, 5V, and +/- 12V. Each site can be configured for any one of the following modes of operation:
PMC: PCI 2.3 in 32-bit or 64-bit mode @ 33MHz or 66MHz PCI-X in 64-bit mode @ 66MHz or 133MHz XMC: Serial RapidIO x4 Aurora (four MGTs)
Mezzanine sites comply with IEEE P1386/P1386.1 CMC/PMC draft standard, ANSI/VITA 20-2001 (R2005), ANSI/VITA 32-2003, ANSI/VITA 35-2000, ANSI/VITA 39-2003, VITA 42.0-2005: drafts VITA 42.2 and VITA 42.5. |
| PMC J4-to-VITA 46 |
The J4 connector on each mezzanine site interfaces to the VITA 46 MGT backplane connector. |
| Serial RapidIO ports on VITA-46 P1 |
Four independent, full duplex Serial RapidIO x4 ports on the VITA 46 P1 multi-gig connector in compliance with the VITA 46.3 draft standard.
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| CoSine Compute Nodes |
The MM-1650 is equipped with two independent CoSine Compute Nodes (CCN). Each CCN includes a Xilinx 2VP100 FPGA, Xilinx Virtex-4 LX160, two PowerPC processors, one Primary DDR array, two PowerPC local DDR arrays, four banks of QDR II SRAM, two PowerPC Flash arrays, and FPGA platform Flash arrays.
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| PowerPC Processors |
Each CCN contains two independent IBM 405GP PowerPC processors, providing four total processors on the MM-1650. |
| Primary DDR Arrays |
Each multi-ported Primary DDR array can be configured with 256MB, 512MB, or 1GB of DDR memory with ECC per CCN, for a total of up to 2GB on the MM-1650. |
| ECC |
An ECC engine on the Primary DDR array detects and corrects all single-bit errors, detects all double-bit errors, and some three and four bit errors within the same nibble. |
| Processor Local DDR |
Each PowerPC processor has 128MB of local DDR memory. |
| QDR II SRAM |
Each CCN contains 36MB of QDR II SRAM local to the Virtex-4 LX160 for buffering UPL processing operations. |
| FPGA Platform Flash |
Each CCN is equipped with FPGA platform Flash independent to each FPGA for multiple bitstreams and independent reconfiguration. |
| Processor Local Flash |
Each PowerPC has 32MB of processor programmable Flash and is capable of storing multiple boot images. |
| Protected Access |
For security against inadvertent Flash programming or corruption, a hardware switch is provided to disable the write enable line to the Flash devices along with additional high security capabilities. |
| Ethernet |
Each CCN has one 10/100 Ethernet interface shared between the two PowerPCs for SNMP command and control, debug, and downloading remote boot images or bitstreams. |
| On-board Serial RapidIO x4 Connectivity |
On-board crossbar switch provides simultaneous, non-blocking communication for eight independent, full duplex Serial RapidIO x4 ports (two CCN ports, four VITA 46 P1 backplane ports, two optional XMC ports).
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| VME320 Interface |
VME interface supports master/slave VME32, VME64, or VME 2eSST communications. Primary pins on P2 with additional pins on P3, P4, and P5 per VITA 46.0 draft standard |
| Debug Ports |
Debug ports include four RS-232 UART consoles, one board/system push button reset switch, and two processor JTAG debug ports. Debug ports are available out the front panel or backplane. |
| Status Indicators |
Four front panel LEDs indicate Ethernet and CCN status. Each CoSine LED is software programmable. |
| Power Rails |
+5V, +12V/+48V, +/-12V supply. Contact factory for specific power requirements. |
| Physical Dimensions |
Height: 233.4 mm (9.2 in.) Depth: 160 mm (6.3 in.) Front Panel Height: 261.8 mm (10.3 in.) |
Width: 19.8 mm (0.8 in.) Max. Component Height: 14.8 mm (0.58 in.) |
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