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Vanguard PCI
Bus Analyzer, Exerciser, Protocol Checker & Compliance Checker for PCI and PCI-X
- Networked Bus Analyzer (built-in Ethernet port)
- 0-133 MHz PCI-X and 0-67 MHz PCI
- 2 MSample Trace Buffer at 256 bits
- Concurrent and independent operation of all functions
- Protocol Checker and Exerciser
The Vanguard PCI Bus Analyzer is a complete solution for PCI/PCI-X debug, analysis, exercising, protocol detection, and compliance checking.
It includes a 10/100 Mbit/s Ethernet interface, taking the power and flexibility found in Curtiss-Wright's range of Bus Analyzers to unprecedented levels of productivity. The bus analyzer is controlled from a PC running Windows and BusView graphical user interface or an Application Programming Interface (API).
The Vanguard PCI Analyzer supports the PCI and PCI-X protocol and signaling. The PCI, PCI0SL and CompactPCI form factors share a common hardware module, called the SAM (State Analyzer Module) module, which is interchangeable between the carrier boards.
State Analyzer
The State Analyzer of the Vanguard PCI captures and displays 64- or 32-bit PCI-X/PCI bus activity up to 133 MHz with highly advanced (yet simple to use) triggering, filtering and counting capabilities. To provide optimum bus analysis for a given problem, the state analyzer offers a choice of three sampling modes, i.e. Standard Mode, Clock Mode & Transfer Mode.
Exercisers
The two Exerciser versions (basic and enhanced) available for the Vanguard PCI Analyzer are flexible and easy to use. The Vanguard exercisers allow concurrent operation of two DMA engines, a target memory with I/O and memory spaces, and a command executer. A flexible script feature allows test scripts to be made and tasks to be automated.
Protocol Checker
The product features an optional protocol checker for PCI-X and PCI. This versatile feature automatically detects up to 71 PCI-X and 45 PCI protocol errors, helping the user to track down bus hardware errors without the need to understand the nature of the problem. The protocol checker can run in the background when other analyzer functions of the Vanguard PCI Analyzer are active. As an example, the state analyzer, and the bus utilization statistics can all be active at the same time while the protocol checker runs in the background, screening the bus for errors. If the protocol checker is used as the trigger source for the analyzer(s), the state and timing analyzers will then provide a comprehensive picture of the bus activity around the point when an error was found. This helps the user to identify and correct the problem.
| General | | | PCI-X/PCI bus | 32/64-bit, up to 133 MHz | | Interfaces | | | USB port | 12 Mb/s | | Ethernet port | 10/100 Mb/s | | Power supply requirements | +3.3VDC +/-5% from PCI backplane or from ext. power supply via front panel inlet. | | Power consumption | 1.8A (6W) idle. 5A (16.7W) max | | Dimensions | 174.6 x 106.7mm (Short card) One PCI slot | | Compliant to | PCI Rev. 2.3
PCI-X rev. 1.0a | | Measurements | Temperature probe: 0-120 °C / 32-248 °F
Voltage: 3.3V, 5V, 12V | | Operating temperature | 0-50 °C/ 32-122 °F | | | | | Analyzer | | | Trace Memory | 2M Samples x 256 bits (64 MBytes total) | | Input channels | 92 bus signals, plus 16 ext. inputs on pin headers | | PCI-X/PCI clock requirements | Max. 133 MHz, min. 1 kHz | | Signal levels | 3.3V or 5V (using included adapter) | | Monitored signals | AD[31::0], AD[63::32], C/BE[3::0]#, C/BE[7::4]#, FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, PAR, PAR64, PERR#, SERR#, RST#, INTA:D#, LOCK#, ACK64#, REQ64#, REQ#, GNT#, IDSEL, (Plus GNT3:0#, REQ3:0#, IDSEL via pin headers) | | Trigger | 8 word recognizers covering all 93 PCI signals and 16 Ext. inputs. True Range & NOT operator on Address/Data. Edge Triggering. | | Range | 8 A64 address ranges, 8 D64 data ranges. Inside/Outside. | | Sequencer | 16 levels with If, Else, Elsif, Goto, Count, Delay, Trigger, Store, Halt. | | Trigger position | 0-100%, 1% resolution | | Occurrence / delay counters | 3 x 32-bits | | Event counters | 8 x 30-bits for Statistics | | Real-Time Statistics Counters | 47 x 30-bits counters | | Decode Speed Counter | 1 dedicated counter | | Time Tag | Range: 30ns-4688min@33MHz, 15ns-2344min30sec@66MHz, 10ns-1562 min@100MHz, 7.5ns-1172min@133MHz
Resolution: 30ns@33MHz, 15ns@66MHz, 10ns@100MHz, 7.5ns@133MHz | | Latency Tag | Counts latency (wait states) from FRAME# to TRDY# asserted. Max count: 64 clocks. | | Trigger Output | LVTTL level trigger output with programmable polarity, level or pulse. May pulse on each stored sample. Available on pin header in front panel. | | External Inputs | 15 TTL level inputs on pin header on back panel. 1 TTL level input on front panel | | | | | Exerciser | | | Master | Zero-wait-states, 1 GB/s @133 MHz peak burst rate, 64-bits Address (PCI-X only), 2 DMA Controllers. | | Target | 8 MB SDRAM memory, 1 GB/s peak burst rate @133 MHz. 32/64-bit address. 256 byte I/O space memory. | | | | | Protocol Checker | | | PCI-X Violations | 71 Protocol Violations | | PCI Violations | 45 Protocol Violations | | |
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